Semiconductor manufacturing processes include many techniques for forming and isolating portions of the semiconductor substrate. One such process is the formation of through-silicon vias (“TSVs” or “vias”) for 3D integration. These vias provide electrical connections vertically between stacked layers of an integrated circuit die. One benefit of vertical connections is the a shorter interconnect length as compared to horizontal interconnections, which can improve device speed. The vias may be made in several ways including via first, via middle, or via last, which indicate when in the chip processing the via is made. Via first describes the formation of vias during front-end fabrication in which the vias are often formed prior to the formation of a transistor. In via middle, or interconnect TSV, the metal-filled TSVs may be added after the transistor has been finished. For via last, the vias are formed on the device side of the substrate after CMOS/BEOL, and the substrate may be bonded to a carrier wafer for the via formation.
The vias are filled with a conductive material, such as copper or tungsten, and may include a liner layer or layers of a dielectric material to help insulate the conductor from the silicon substrate. As semiconductor devices continue to shrink in size and grow in complexity, the allowable tolerances for error within the devices shrink as well. If the metal is not properly insulated, it may migrate and potentially affect device performance with junction leakage or shift in threshold voltage. Thus, a liner layer capable of maintaining and controlling the metal becomes even more important. Moreover, with trenches that may be orders of magnitude larger than other types of trenches, adhesion and deposition issues with the liner layers may be presented that would not occur in smaller scale trenches, such as those formed during transistor processing. Another issue is with moisture inclusion in the liner. If the moisture escapes, the liner may be more porous, and again more prone to allowing metal migration. As vias continue to shrink in width along with the liner used, these problems may become amplified.
Thus, there is a continued need for improved liners and liner-formation techniques to contain the conductive material used in TSVs. These and other needs are addressed by the present technology.